Περιοδικά

• E. Paparsenos and Y. Tsiatouhas, “Radiation-hardened latch design with triple-node-upset recoverability,”
       Elsevier, International Journal of Electronics and Communications, vol. 187, pp. , Dec. 2024.

• H-M. Dounavi and Y. Tsiatouhas, “An aging monitoring scheme for SRAM decoders,”
       Elsevier, Integration: the VLSI Journal, vol. 88, pp. 108-115, 2023.

• S-I. Poulis, G. Papatheodorou, C. Papaioannou, Y. Sfikas, M. E. Plissiti, A. Efthymiou, J. Liaperdos and Y. Tsiatouhas, “Effective Current Pre-Amplifiers for Visible Light Communication (VLC) Receivers,”
       MDPI, Technologies, vol. 10,36, 2022.

• V. Gerakis, Y. Tsiatouhas and A. Hatzopoulos, “A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs,”
       Springer, Journal of Electronic Testing: Theory and Applications, vol. 37, pp. 191-203, 2021.

• H-M. Dounavi, Y. Sfikas and Y. Tsiatouhas, “Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier,”
       Springer, Journal of Electronic Testing: Theory and Applications, vol. 37, pp. 65-82, 2021.

• H-M. Dounavi, Y. Sfikas and Y. Tsiatouhas, “Periodic Monitoring of BTI Induced Aging in SRAM Sense Amplifiers,”
       IEEE Transactions on Device and Materials Reliability, vol. 19, no. 1, pp. 64-72, 2019.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “State Reduction for Efficient Digital Calibration of Analog/RF Integrated Circuits"
       Springer, Analog Integrated Circuits and Signal Processing, vol. 90, no. 1, pp. 65-79, 2017.

• Y. Sfikas and Y. Tsiatouhas, “Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs,”
       IEEE Transactions on Computers, vol. 65, no. 7, pp. 2339-2345, 2016.

• S. Valadimas, Y. Tsiatouhas and A. Arapoyanni, “Timing Error Tolerance in Small Core Designs for SoC Applications,”
       IEEE Transactions on Computers, vol. 65, no.2, pp. 654-663, 2016.

• K. Katsarou and Y. Tsiatouhas, “Soft Error Interception Latch: A Double Node Charge Sharing SEU Tolerant Design,”
       IET Electronics Letters, vol. 51, no. 4, pp. 330-332, 2015.

• S. Matakias, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “A Current Monitoring Technique for IDDQ Testing in Digital Integrated Circuits,”
       Elsevier, Integration the VLSI Journal, vol. 50, no. 1, pp. 48-60, 2015.

• R. Wang, Z. Zang, X. Kavousianos, Y. Tsiatouhas and K. Chakrabarty, “Built-In Self-Test, Diagnosis and Repair of Multi-Mode Power Switches,”
       IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no.8, pp. 1231-1244, 2014.

• E. Arvaniti and Y. Tsiatouhas, “Low Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique,”
       Springer, Journal of Electronic Testing: Theory and Applications, vol. 30, pp. 329-341, 2014.

• Y. Sfikas, Y. Tsiatouhas and S. Hamdioui, “Layout-Based Refined NPSF Model for DRAM Characterization and Testing,”
       IEEE Transactions on VLSI Systems, vol. 22, no. 6, pp. 1446-1450, 2014.

• S. Valadimas, A. Floros, Y. Tsiatouhas, A. Arapoyanni and X. Kavousianos, “The Time Dilation Technique for Timing Error Tolerance,”
       IEEE Transactions on Computers, vol. 63, no.5, pp. 1277-1286, 2014.

• Z. Zang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas, “Static Power Reduction using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches,”
       IEEE Transactions on VLSI Systems, vol. 22, no. 1, pp. 13-26, 2014.

• S. Valadimas, Y. Tsiatouhas, A. Arapoyanni and P. Xarchakos, “Effective Timing Error Tolerance in Flip-Flop Based Core Designs,”
       Springer, Journal of Electronic Testing: Theory and Applications, vol. 29, pp. 795-804, 2013.

• C. Efstathiou, Z. Owda and Y. Tsiatouhas, “New High Speed Multi-Output Carry Look-Ahead Adders,”
       IEEE Transactions on Circuits and Systems-II, vol. 60, no. 10, pp. 667-671, 2013.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “Adjustable RF Mixers’ Alternate Test Efficiency Optimization by the Reduction of Test Observables,”
       IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no.9, pp. 1383-1394, 2013.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “A Test and Calibration Strategy for Adjustable RF Circuits,”
       Springer, Analog Integrated Circuits and Signal Processing, vol. 74, no.1, pp. 175-192, 2013.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “A Bult-In Voltage Measurement Technique for the Calibration of RF Mixers,”
       IEEE Transactions on Instrumentation and Measurement, vol. 62, no.4, pp. 732-742, 2013.

• L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “A Bult-In-Test Circuit for RF Differential Low Noise Amplifiers,”
       IEEE Transactions on Circuits and Systems - I, vol. 57, no.7, pp. 1549-1558, 2010.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Current Mode, Parallel, Two-Rail Code Checker,”
       IEEE Transactions on Computers, vol. 57, no.8, pp. 1032-1045, 2008.

• Th. Haniotakis, Y. Tsiatouhas, D. Nikolos and C. Efstathiou, “Testable Designs of Multiple Precharged Domino Circuits,”
       IEEE Transactions on VLSI Systems, vol. 15, no. 4, pp. 461-465, 2007.

• Y. Tsiatouhas, “A Stress-Relaxed Negative Voltage-Level Converter,”
       IEEE Transactions on Circuits and Systems - II, vol. 54, no. 3, pp. 282-286, 2007.

• K. Limniotis, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Design Technique for Energy Reduction in NORA CMOS Logic,”
       IEEE Transactions on Circuits and Systems - I, vol. 53, no. 12, pp. 2647-2655, 2006.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs,”
       Journal of Electronic Testing: Theory and Applications, vol. 20, no. 5, pp. 517-525, 2004.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators,”
       Journal of Electronic Testing: Theory and Applications, vol. 20, no. 2, pp. 133-142, 2004.

• Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou and D. Nikolos, “Domino-CMOS Strongly Code Disjpoint and Strongly Fault Secure 2-out-of-3 and 1-out-of-3 Code Checkers,”
       International Journal of Electronics, vol. 90, no.2, pp. 145-158, 2003.

• Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D. Nikolos and A. Arapoyanni, “A New Technique for I_DDQ Testing in Nanometer Technologies,”
       Integration the VLSI Journal, vol. 31, pp. 183-194, 2002.

• A. Chrisanthopoulos, Y. Moisiadis, Y. Tsiatouhas and A. Arapoyanni, “Comparative Study of Different Current Mode Sense Amplifiers in Submicron CMOS Technology,”
       IEE Proceedings on Circuits, Devices and Systems, vol. 149, no. 3, pp. 154-158, 2002.

• H.T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and M. Nicolaidis, “On Path Delay Fault Testing of Multiplexer-Based Shifters,”
       International Journal of Electronics, vol. 88, no. 8, pp. 923-937, 2001.

• G. Kamoulakos, Y. Tsiatouhas, A. Chrisanthopoulos and A. Arapoyianni, “A High –Density DRAM Cell with Built-In Gain Stage,”
       IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1194-1199, 2001.

• G. Kamoulakos, Th. Haniotakis, Y. Tsiatouhas, J-P. Schoellkopf and A. Arapoyianni, “Device Simulation of an n-DMOS Cell with Trench Isolation,”
       Microelectronics Journal, vol. 32 (1), pp. 75-80, 2001.

• G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas and A. Arapoyanni, “Management of Charge Pump Circuits,”
       Integration the VLSI Journal, vol. 30 (1), pp. 91-101, 2000.

• Y. Tsiatouhas, Th. Haniotakis, D. Nikolos, A Paschalis and C. Halatsis, “Hierarchical Robust Test Generation for CMOS Circuit Stuck-Open Faults,”
       International Journal of Electronics, vol. 82, no. 1, pp. 45-60, 1997.

• Y. Tsiatouhas, Th. Haniotakis, C. Halatsis and A. Arapoyanni, “Design of Stuck-Open Fault Testable CMOS Complex Gates,”
       IEE Electronics Letters, vol. 32, no. 4, pp. 315-317, 1996.

• Y. Tsiatouhas, A. Paschalis, D. Nikolos and C. Halatsis, “Robust Test Generation for Transistor Stuck-Open Faults in CMOS Complex Gates,”
       International Journal of Electronics, vol. 79, no. 2, pp. 129-142, 1995.

Συνέδρια

• D. Georgoulas, Y. Tsiatouhas and V. Tenentes, “CAS-PUF: Current-mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCs,”
       Accepted at Design, Automation and Test in Europe Conference (DATE), Mar. 2025.

• E. Paparsenos and Y. Tsiatouhas, “Triple-Node-Upset Recoverable Radiation-Hardened by Design Latch,”
       Panhellenic Conference on Electronics and Telecommunications (PACET), Mar. 2024.

• S. Spyridonos and Y. Tsiatouhas, “Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories,”
       Design, Automation and Test in Europe Conference (DATE), Mar. 2024.

• M. E. Plissiti, C. Papaioannou, Y. Sfikas, G. Papatheodorou, S-I. Poulis, A. Efthymiou and Y. Tsiatouhas, “Deep learning based detection of anti-reflective obstacles in VLC systems,”
       International Conference on Artificial Intelligence in Information and Communication (ICAIIC), Feb. 2024.

• C. Dilopoulou and Y. Tsiatouhas, “BTI Aging Influence in SRAM-based In-Memory Computing Schemes and its Mitigation,”
       30th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2023.

• C. Dilopoulou and Y. Tsiatouhas, “BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs,”
       12th International Conference on Modern Circuits and Systems Technologies (MOCAST), June 2023.

• A. Xynos, V. Tenentes and Y. Tsiatouhas, “SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs,”
       IEEE European Test Symposium (ETS), May. 2023.

• C. Efstathiou, L. Agalioti and Y. Tsiatouhas, “Efficient Dynamic Logic Magnitude Comparators,”
       30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct. 2022.

• S. Spyridonos and Y. Tsiatouhas, “BTI Aging Influence on Charge Pump Circuits,”
       11th International Conference on Modern Circuits and Systems Technologies (MOCAST), Sept. 2022.

• C. Papaioannou, M. E. Plissiti, Y. Sfikas, G. Papatheodorou, S-I. Poulis, A. Efthymiou and Y. Tsiatouhas, “Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles,”
       IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom), June 2022.

• M. E. Plissiti, C. Papaioannou, Y. Sfikas, G. Papatheodorou, S-I. Poulis, A. Efthymiou and Y. Tsiatouhas, “An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems,”
       IEEE International Mediterranean Conference on Communications and Networking (MeditCom), September 2021.

• V. Gerakis, Y. Tsiatouhas and A. Hatzopoulos, “An Alternative Post-bond Testing Method for TSVs,”
       9th International Conference on Modern Circuits and Systems Technologies (MOCAST), September 2020.

• H-M. Dounavi, Y. Sfikas and Y. Tsiatouhas, “Monitoring of BTI and HCI Aging in SRAM Decoders,”
       IEEE European Test Symposium (ETS), May 2020.

• C. Efstathiou, and Y. Tsiatouhas, “On the Static CMOS Implementation of Magnitude Comparators,”
       IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), Accepted, Jul. 2019.

• C. Efstathiou, K. Dimolikas, C. Papaioannou and Y. Tsiatouhas, “Low Power and High Speed Static CMOS Digital Magnitude Comparators,”
       IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 249-252, Dec. 2018.

• H-M. Dounavi, Y. Sfikas and Y. Tsiatouhas, “Periodic Aging Monitoring in SRAM Sense Amplifiers,”
       IEEE Symposiun on On-Line Testing and Robust System Design (IOLTS), July 2018.

• H-M. Dounavi, Y. Sfikas and Y. Tsiatouhas, “Aging Monitoring in SRAM Sense Amplifiers,”
       7th International Conference on Modern Circuits and Systems Technologies (MOCAST), May 2018.

• S-G. Papadopoulos, V. Gerakis, Y. Tsiatouhas and A. Hatzopoulos, “Oscillation-based Technique for Post-Bond Parallel Testing and Diagnosis of Multiple TSVs,”
       27th International Symposiun on Power and Timing Modeling, Optimization and Simulation (PATMOS), Sept. 2017.

• Y. Sfikas and Y. Tsiatouhas , “Variation Tolerant BTI Monitoring in SRAM Cells,”
       IEEE Symposiun on On-Line Testing and Robust System Design (IOLTS), July 2017.

• Y. Tsiatouhas, “Periodic Bias-Temperature Instability Monitoring in SRAM Cells,”
       IEEE European Test Symposium (ETS), May 2017.

• S. Valadimas, Y. Tsiatouhas and A. Arapoyanni, “Timing Error Mitigation in Microprocessor Cores,”
       IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 772-775, Dec. 2016.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “Improved Alternate Test Accuracy Using Weighted Training Sets,”
       Proc. of the XXXI Conference on Design of Circuits and Integrated Systems (DCIS), Nov. 2016.

• R. Katreepali, H. Chemanchula, Th. Haniotakis and Y. Tsiatouhas, “Low-power and High Performance Sinusoidal Clocked Dynamic Circuit Design,”
       IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp., July 2016.

• K. Katsarou and Y. Tsiatouhas, “Soft Error Immune Latch Under SEU Related Double-Node Charge Collection,”
       IEEE International On-Line Testing Symposium (IOLTS), pp. 46-49, July 2015.

• Y. Sfikas, Y. Tsiatouhas, M. Taouil and S. Hamdioui, “On Resistive Open Defect Detection in DRAMs: The Charge Accumulation Effect,”
       IEEE European Test Symposium (ETS), pp. , May 2015.

• A. Anastasiou, Y. Tsiatouhas and A. Arapoyanni, “On the Reuse of Existing Error Tolerance Circuitry for Low Power Scan Testing,”
       IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1578-1581, May 2015.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “A Method for the Estimation of Defect Detection Probability of Analog/RF Defect-Oriented Tests,”
       IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 1395-1400, Mar. 2015.

• J. Liaperdos, H.G. Stratigopoulos, L. Abdallah, Y. Tsiatouhas, A. Arapoyanni and X. Li, “Fast Deployment of Alternate Analog Test Using Bayesian Model Fusion,”
       IEEE/ACM Design Automation and Test in Europe Conference (DATE), pp. 1030-1035, Mar. 2015.

• K. Katsarou and Y. Tsiatouhas, “Double Node Charge Sharing SEU Tolerant Latch Design,”
       IEEE International On-Line Testing Symposium (IOLTS), pp. 122-127, July 2014.

• A. Anastasiou and Y. Tsiatouhas, “Power Efficient Scan Testing by Exploiting Existing Error Tolerance Circuitry in a Design,”
       IEEE European Test Symposium (ETS), pp. 221-222, May 2014.

• H-M. Dounavi and Y. Tsiatouhas, “Stuck-at Fault Diagnosis in Scan Chains,”
       International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 96-101, May 2014.

• K. Katsarou, Y. Tsiatouhas and A. Arapoyanni, “NBTI Aging Tolerance in Pipeline Based Designs,”
       IEEE International On-Line Testing Symposium (IOLTS), pp. 31-36, July 2013.

• M. Chalkia and Y. Tsiatouhas, “The Leafs Scan-Chain for Test Application Time and Scan Power Reduction,”
       IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 749-752, Dec. 2012.

• S. Valadimas, Y. Tsiatouhas, A. Arapoyanni and A. Evans, “Single Event Upset Tolerance in Flip-Flop Based Microprocessor Cores,”
       16^th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 79-84, Oct. 2012.

• I. Voyiatzis, C. Efstathiou, Y. Tsiatouhas and C. Sgouropoulou, “A Novel Architecture to Reduce Test Time in March-Based SRAM Tests,”
       International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), p. A-1.2 , May 2012.

• S. Valadimas, Y. Tsiatouhas and A. Arapoyanni, “Cost and Power Efficient Timing Error Tolerance in Flip-Flop Based Microprocessor Cores,”
       IEEE European Test Symposium (ETS), pp. 8-13, May 2012.

• E. Arvaniti and Y. Tsiatouhas, “Low Power Scan by Partitioning and Scan Hold,”
       IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), pp. 262-265, April 2012.

• Y. Sfikas and Y. Tsiatouhas, “Efficiemt DRAM Memory Testing Algorithms,”
       Panhellenic Conference on Electronics and Telecommunications, (PACET), March 2012.

• J. Liaperdos, L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “Fault Detection in RF Mixers Combining Defect-Oriented and Alternate Test Strategies,”
       26^th Conference on Design of Circuits and Integrated Systems (DCIS), pp. 315-320, Nov. 2011.

• Z. Zang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas, “A BIST Scheme for Testing and Repair of Multi-Mode Power Switches,”
       IEEE International On-Line Testing Symposium (IOLTS), pp. 133-138, July 2011.

• Z. Owda, Y. Tsiatouhas, and Th. Haniotakis, “High Performance and Low Power Dynamic Circuit Design,”
       IEEE International NEWCAS Conference (NEWCAS), pp. 502-505, June 2011.

• Z. Zang, X. Kavousianos, Y. Luo, Y. Tsiatouhas and K. Chakrabarty, “Signature Analysis for Testing, Diagnosis and Repair of Multi-Mode Power Switches,”
       IEEE European Test Symposium (ETS), pp. 13-18, May 2011.

• J. Liaperdos, L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “A Test Technique and a BIST Circuit to Detect Catastrophic Faults in RF Mixers,”
       International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), April 2011.

• Z. Zang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas, “A Robust and Reconfigurable Multi-Mode Power Gating Architecture,”
       International Conference on VLSI Design (VLSID), Jan. 2011.

• S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, “Timing Error Tolerance in Nanometer ICs,”
       16^th IEEE International On-Line Testing Symposium (IOLTS), pp. 283-288, July 2010.

• Y. Moisiadis and Y. Tsiatouhas, “A Receiver Circuit for Low-Swing Interconnect Schemes,”
       IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010.

• Th. Haniotakis, Z. Owda and Y. Tsiatouhas, “Memory-less Pipeline Dynamic Circuit Design Technique,”
       IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2010.

• L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “A Build-In Self-Test Technique for RF Mixers,”
       IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), pp. 88-92, April 2010.

• Y. Sfikas and Y. Tsiatouhas, “Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing,”
       IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), pp. 108-113, April 2009. (Best Paper Award)

• A. Floros, Y. Tsiatouhas and X. Kavousianos, “The Time Dilation Scan Architecture for Timing Error Detection and Correction,”
       IFIP/IEEE International Conference on Very Large Scale Integration, (VLSI-SoC), pp. 569-574, October 2008.

• I. Fudos, X. Kavousianos, D. Markouzis and Y. Tsiatouhas, “Placement and Routing in Computer Aided Design of Standard Cell Arrays by Exploiting the Structure of the Interconnection Graph,”
       Computer-Aided Design Conference, (CAD), pp. 325-337, June 2008.

• Y. Tsiatouhas, A. Arapoyanni and D. Skias, “A Scan Flip-Flop for Low-Power Scan Operation,”
       IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 439-442, December 2007.

• A. Floros, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism,”
       IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 692-695, December 2006.

• Y. Tsiatouhas and A. Arapoyanni, “High Fan-In Differential Current Mirror Logic,”
       IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3894-3897, May 2006.

• S. Matakias, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “An Embedded I_DDQ Testing Circuit and Technique,”
       12^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2005.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Design for Testability Technique for Differential RF Low Noise Amplifiers,”
       XX Conference on Design of Circuits and Integrated Systems (DCIS), November 2005.

• S. Matakias, Y. Tsiatouhas, A. Arapoyanni, Th. Haniotakis, G. Prenat and S. Mir, “A Built-In I_DDQ Testing Circuit,”
       31^st IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 471-474, September 2005.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni and A. Efthimiou, “Fast, Parallel Two-Rail Code Checker with Enhanced Testability,”
       11^th IEEE International On-Line Testing Symposium (IOLTS), pp. 149-156, July 2005.

• A. Rao, Th. Haniotakis, Y. Tsiatouhas, and H. Djemil, “The Use of Pre-evaluation Phase in Dynamic CMOS Logic,”
       IEEE Computer Scociety Annual Symposium on VLSI (ISVLSI), pp. 270-271, May 2005.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Built-In Self Test Scheme for Differential Ring Oscillators,”
       6^th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 448-452, March 2005.

• A. Rao, Th. Haniotakis, Y. Tsiatouhas, and V. Kaky, “A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations,”
       10^th IEEE On-Line Testing Symposium (IOLTS), pp. 52-57, July 2004.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications,”
       IEEE Symposium on VLSI (ISVLSI), pp. 293-296, February 2004.

• Y. Tsiatouhas, K. Limniotis, A. Arapoyanni, and Th. Haniotakis, “A Low Power NORA Circuit Design Technique Based on Charge Recycling,”
       10^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 224-227, December 2003.

• Y. Tsiatouhas, S. Matakias, A. Arapoyanni, and Th. Haniotakis, “A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs,”
       9^th IEEE International On-Line Testing Symposium (IOLTS), pp.12-16, July 2003.

• Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “An Embedded I_DDQ Testing Architecture and Technique,”
       4^th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 442-445, March 2003.

• A. Chrisanthopoulos, Y. Tsiatouhas, A.Arapoyanni and Th. Haniotakis, “SRAM Oriented Memory Sense Amplifier Design in 0.18um CMOS Technology,”
       IEEE International Symposium on Circuits and Systems (ISCAS), pp. V: 145-148, May 2002.

• Y. Tsiatouhas, Th. Haniotakis, D.Nikolos and A. Arapoyanni, “Extending the Viability of I_DDQ Testing in the Deep Submicron Era,”
       3^rd IEEE International Symposium on Quality Electronic Design (ISQED), pp. 100-105, March 2002. (Best Paper Award)

• A. Chrisanthopoulos, Th. Haniotakis, Y.Tsiatouhas and A. Arapoyanni, “New Test Pattern Generation Units for NPSF Oriented Memory Built-In Self Test,”
       8^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 749-752, September 2001.

• A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y.Tsiatouhas and A. Arapoyanni, “A New Flash Memory Sense Amplifier in 0.18um CMOS Technology,”
       8^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 941-944, September 2001.

• Y. Tsiatouhas, A. Chrisanthopoulos, G. Kamoulakos, and Th. Haniotakis, “New Memory Sense Amplifier Designs in CMOS Technology,”
       7^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 19-22, December 2000.

• D. Skias, Th. Haniotakis, Y. Tsiatouhas and A. Arapoyanni, “A State Assignment Algorithm for Finite State Machines,”
       7^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 823-826, December 2000.

• Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and A. Arapoyanni, “A Versatile Built-In Self Test Scheme for Delay Fault Testing,”
       ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp. 756, March 2000.

• Th. Haniotakis, D. Nikolos, G. Sidiropoulos, Y. Tsiatouhas and H.T. Vergos, “A Class of Easily Path Delay Fault Testable Circuits,”
       IEEE Southwest Symposium on Mixed-Signal Design (SSMSD), pp. 165-170, Feb. 2000.

Workshops

• L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni and A Karagounis, “A Built-In Test Circuit for RF Single Ended Low Noise Amplifiers,”
       IEEE North Atlantic Test Workshop (NATW), May 2008.

• S. Matakias, Y. Tsiatouhas, A. Arapoyianni, and Th. Haniotakis, “ A High Speed Circuit for Concurrent Detection of Soft Errors in CMOS ICs,”
       Workoshop on Radiation Effects on Components and Systems (RADECS), Sept. 2006.

• Y. Tsiatouhas, A. Arapoyanni, D. Nikolos and Th. Haniotakis, “A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing,”
       8^th IEEE International On-Line Testing Workshop (IOLTW), pp. 56-60, July 2002.

• Y.Tsiatouhas, Th. Haniotakis, D. Nikolos and C. Efstathiou, “Concurrent Detection of Soft Errors Based on Current Monitoring,”
       7^th IEEE International On-Line Testing Workshop (IOLTW), pp. 106-110, July 2001.

• Y. Tsiatouhas, Th. Haniotakis and D.Nikolos, “A Compact Built-In Current Sensor for I_DDQ Testing,”
       6^th IEEE International On-Line Testing Workshop (IOLTW), pp. 95-99, July 2000.

• Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D.Nikolos and A. Arapoyanni, “A New Scheme for Effective I_DDQ Testing in Deep Submicron,”
       6^th IEEE International Workshop on Defect Based Testing (DBT), pp. 9-14, April 2000.

Τελευταία Ενημέρωση: Οκτώβριος 2024