CS-UOI VLSI Technology and Computer Architecture Lab CS-UOI
 

IOLTS - 2010

Timing Error Tolerance in Nanometer ICs

Stefanos Valadimas
University of Athens (GR)
Yiorgos Tsiatouhas
University of Ioannina (GR)
Angela Arapoyanni
University of Athens (GR)

IEEE International On-Line Testing Symposium, July 2010, pp. 283-288

Keywords: Timing failures, Timing errors, Error detection and correction, Timing error tolerance

ABSTRACT
Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.

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UOI  University of Ioannina - Dept. of Computer Science