CS-UOI VLSI Technology and Computer Architecture Lab CS-UOI
 

VLSI-SoC - 2008

The Time Dilation Scan Architecture for Timing Error Detection and Correction

Andreas Floros
University of Ioannina (GR)
Yiorgos Tsiatouhas
University of Ioannina (GR)
Xrysovalantis Kavousianos
University of Ioannina (GR)

IFIP/IEEE International Conference on Very Large Scale Integration, Oct. 2008, pp. 569-574

Keywords: On-Line Testing, Concurrent Testing, Error Detection and Correction, Time Dilation Technique

ABSTRACT
Timing failures in high complexity - high frequency circuit designs, which are mainly caused by test escapes and environmental as well as operating conditions, are a real concern in nanometer technologies. In this work, the Time Dilation (TimeD) scan architecture is proposed, which is suitable for both concurrent error detection/correction and off-line testing. The TimeD architecture offers concurrent multiple error detection and correction at the small penalty of one clock cycle delay at the normal circuit operation for each error correction. Moreover, it has lower silicon area requirements compared to previous techniques, and it imposes negligible overhead on the circuit performance.

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UOI  University of Ioannina - Dept. of Computer Science