CS-UOI VLSI Technology and Computer Architecture Lab CS-UOI
 

DDECS - 2009

Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing

Yiorgos Sfikas
University of Ioannina (GR)
Yiorgos Tsiatouhas
University of Ioannina (GR)

IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 2009, pp. 108-113

Keywords: Memory Testing, DRAM Testing, Neighborhood Pattern Sensitive Fault (NPSF) Testing, Δ-Type Neighborhood

ABSTRACT
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated with it, compared to other fault models, restricts its wide adoption for memory testing. In this work we exploit the physical design (layout) of folded DRAM memory arrays to introduce a new neighborhood type for NPSF testing and a pertinent test and locate algorithm. This algorithm reduces drastically the test application time (about 58% with respect to the well known Type-1 neighborhood) aiming to make the NPSF model also a cost attractive choice. In addition, we introduce the Neighborhood Word-Line Sensitive Fault model and the corresponding test algorithm to cover those faults along with NPSFs, achieving test application time cost reduction from 33% to 41%, depending on various assumptions, with respect to the Type-1 neighborhood.

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UOI  University of Ioannina - Dept. of Computer Science