VLSI Technology and Computer Architecture Lab CS-UOI
 

ESSCIRC - 2005

A Built-In IDDQ Testing Circuit

Sotiris Matakias
University of Athens (GR)
Yiorgos Tsiatouhas
University of Ioannina (GR)
Angela Arapoyanni
University of Athens (GR)
Themistoklis Haniotakis
Southern Illinois University (USA)
Guillaume Prenat
TIMA Lab (FR)
Salvador Mir
TIMA Lab (FR)

IEEE European Solid-State Circuit Conference, Sept. 2005, pp. 471-474

Keywords: IDDQ Testing, Built-In Current Sensor (BICS)

ABSTRACT
Although IDDQ testing has become a widely accepted defect detection technique for CMOS ICs, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, a built-in IDDQ testing circuit is presented, that aims to extend the viability of IDDQ testing in future technologies and first experimental results are discussed.

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UOI  University of Ioannina - Dept. of Computer Science