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The
course "Digital Design II" is taught in the fall
semester. The main goal of the course is the design and implementation of High
Performance Integrated Circuits using Computer Aided Design toos. The course
consists of two parts:
Suggested
Books
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Digital Design: An Embedded Systems Approach Using
VHDL |
ΨΗΦΙΑΚΑ ΣΥΣΤΗΜΑΤΑ,
Μοντελοποίηση & Προσομοίωση με τη
γλώσσα VHDL |
Fundamentals of Digital Logic with VHDL Design |
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Peter J. Ashenden |
Σουραβλάς Σταύρος Ι.
Ρουμελιώτης Μάνος |
Brown S., Vranesic Ζ. |
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information...) |
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information...) |
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Theory In
12 lectures the elementary disciplines of Digital System design using CAD tools are
presented. Every lecture is 3-hours long. The most important goal is the design
of VLSI systems using VHDL. The general flow of IC implementation is also
briefly introduced.
Laboratory Exercises The
laborator exercises are optional and their main goal is the better understanding
of the theory with emphasis on the design of systems and the programming of FPGA
devices. The exercises are very simple and provide the elementary know-how
to the students who attend them (the duration of every lab exercise is 2-3 hours).
Every student can attend 1 up to 8 exercises. In every exercise the student has
to be physically present and to prepare a report which is evaluated from the
instructor. The students who attend the lab may earn up to 3 grades (depending
on the evaluation of the reports). There are 2 more optional exercises which
offer a bonus grade. The lab grades are given after an oral examination (if this
is necessay)!
Course Material
The course material is included in the lesson-notes
which are distributed to the students. Additionally, three books are suggested
to improve the student's skills on VHDL. The topics covered are the following:
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Circuit Design with CAD-tools
(Front End): Design Entry, Schematic Design, HDLs.
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Elementary Circuits, Basic Arithmetic Circuits (DataPaths):
Adders, Multipliers.
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Circuit Design using VHDL.
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Back End: Partitioning, Floorplaning,
Placement, Routing.
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System Design on FPGAs: Architectures,
Families, Examples
Lectures
| Design Entry |
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| Elementary & Arithmetic Circuits |
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| Algorithmic State Machines |
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| VHDL |
| Introduction in VHDL |
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| Data Types |
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| Sequential Instructions |
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| Advanced Types (VHDL) |
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| Basic Modelling Structures |
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| Subroutines-Packages |
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| Gate Level Modelling |
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| Simulation |
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| Design with VHDL |
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| Designing
Topics |
| Back End |
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| Programmable Devices |
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| Memories |
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| Input - Output |
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Grades
Laboratory exercises offer up to 4/10 grades (3/10
grades offer the first eight exercises and 1 grade the last two). The student
passes the exam when the test grade plus the 1/3 of the lab grade is greater
than 5.
The final grade on the course is calculated as
follows:
Final Grade = Written Exam Grade +
Laboratory Exercises Grade
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