The graduate course "Synthesis of Digital Systems" is tought in the winter semester. The objective of the course is the presentation of methods and algorithms for synthesis of electronic systems from Hardware Description Languages (HDL). The master student develops his skills on describing hardware systems and on synthesizing digital systems from HDL to logic elements. The course consists of two parts: 

• Theory: In 14 lectures the basic rules of digital system synthesis are developed. Every lecture is 3-hours long. Supportive matterial is also distributed to students who are unfamiliar with VHDL.

• Project: the student describes a digital system in VHDL and synthesizes the digital system by following the basic steps of synthesis. The synthesis targets are the area and speed optimization of the synthesized circuit. The final system is finally developed in an FPGA board.

Διαλέξεις

The Course
1. Introduction
2. Architectural Models
3. Quality Measures
4. HDLs
5. representations
6. Partitioning
7. Architectural Synthesis
8. Scheduling Algorithms
9.  Data Path Synthesis
10. Control Unit Synthesis
11. Logic Synthesis
12. Critical Path Synthesis
13. Library Binding
14. Synthesis for Low Power

Grades

The student passes the course if he (she) successfully participates to both the theoretical and practical exams.  

The final grade is computed as follows: 

Final Grade = 0.5(Written Exam Grade)+0.5(Project Grade)

provided that:

1. Written Exam Grade >= 5.0

2. Project Grade >= 5.0