Π1.
X. Kavousianos,
D.
Nikolos,
G.
Foukarakis
& T.
Gnardellis,
"New
Efficient Totally Self Checking Berger Code
Checkers", Integration
the VLSI Journal, 28 (1999)
pp.
101-118.
Π2.
X. Kavousianos,
D. Nikolos, G. Sidiropoulos, "Novel
Single and Double Output TSC CMOS Checkers for
m-out-of-n Codes", VLSI Design, vol.
11, No. 1, 2000,
pp.
35-45.
Π3.
D. Bakalis, X. Kavousianos, H. T. Vergos, D.
Nikolos & G. Ph. Alexiou, "Low
Power Built-In Self-Test Schemes for Array and
Booth Multipliers", VLSI
Design, vol. 12, No. 3, 2001, pp. 431-448.
Π4.
E.
Kalligeros
,
X. Kavousianos, D. Bakalis, D. Nikolos,
"On-the-fly
Reseeding: A New Reseeding Technique for
test-per-clock BIST" Journal
of Electronic Testing: Theory and Applications,
Special Issue (On-Line Test), vol. 18, No. 3, June 2002, pp. 315-332.
Π5.
X. Kavousianos,
D. Bakalis, D. Nikolos and S. Tragoudas, "A
new Built-In TPG for Random Pattern Resistant
Faults" IEEE Transactions on Computer
Aided Design of Integrated Circuits and Systems,
vol. 21, No 7, July
2002,
pp.
859-866.
Π6.
E. Kalligeros, X. Kavousianos, D. Nikolos, “Multiphase
BIST: A New Reseeding Technique for High Test Data
Compression”, IEEE Transactions on Computer
Aided Design of Integrated Circuits and Systems,
vol.
23, No 10, Oct. 2004,
pp.
1429-1446.
This
paper is among the 20 most
frequetly downloaded in
year 2004 (http://tcad.polito.it/)
Π7.
X. Kavousianos,
E. Kalligeros, D. Nikolos, “Multilevel
Huffman Coding: An Efficient Test-Data Compression
Method for IP Cores”, IEEE
Transactions on Computer Aided Design of
Integrated Circuits and Systems,
vol. 26, No. 6, June
2007, pp. 1070-1083.
Π8.
X. Kavousianos,
E. Kalligeros
, D. Nikolos, “Optimal
Selective Huffman Coding for Test-Data Compression”,
IEEE
Transactions on Computers, vol.
56, No
8, Aug. 2007, pp.
1146-1152.
Π9.
X. Kavousianos,
E. Kalligeros
, D. Nikolos, "Multilevel-Huffman
Test-Data Compression for IP Cores with Multiple
Scan Chains”, IEEE
Transactions on VLSI Systems, vol. 16, no. 7, July 2008, pp. 926-931.
Π10.
X. Kavousianos,
E. Kalligeros
, D. Nikolos, “Test
Data Compression Based on Variable-to-Variable
Huffman Encoding with Codeword Reusability” IEEE
Transactions on Computer Aided Design of
Integrated Circuits and Systems, vol. 27,
No 7, pp. 1333 - 1338, 2008
Π11.
I. Fudos, X. Kavousianos, D. Markouzis and Y.
Tsiatouhas, “Placement
and Routing in Computer Aided Design of Standard
Cell Arrays by Exploiting the Structure of the
Interconnection Graph”, Computer
Aided Design & Applications, 5(1-4),
325-337, 2008.
Π12.
X. Kavousianos,
D. Bakalis and D. Nikolos, "Efficient
Partial Scan Cell Gating for Low Power Scan-based
Testing", ACM
Transactions on Design Automation of Electronic
Systems, vol 14, No 2, March 2009.
Π13.
V. Tenentes, X. Kavousianos, E. Kalligeros,
"Single and Variable-State-Skip
LFSRs: Bridging the Gap between Test Data
Compression and Test Set Embedding for IP cores",
IEEE Transactions on Computer
Aided Design of Integrated Circuits and Systems
,(to appear).
Π14. X. Kavousianos, V. Tenentes, K. Chakrabarty, E. Kalligeros,
"Defect- Oriented LFSR Reseeding to Target
Unmodeled Defects Using Stuck-at Test Sets", IEEE
Transactions on VLSI Systems,(to appear)
Π15.
X. Kavousianos, K.
Chakrabarty, "Generation of Compact
Stuck-At
Test Sets Targeting Unmodeled Defects", IEEE Transactions on Computer Aided Design of
Integrated Circuits and Systems , vol
30, No 5, pp. 787 - 791, May 2011
Publications
(Conferences)
Σ1.
X.
Kavousianos,
D. Nikolos "Self-Exercising
Self-Testing k-order Comparators", IEEE
VLSI Test Symposium, April 27-May 1, 1997
Monterey, California,
pp.
216-221
Σ2.
D.
Nikolos, X. Kavousianos "A
Totally Self-Checking Error Correcting/ Detecting
Circuit for a Class of SEC/DED/AUED Codes"
IEEE
International On-Line Testing Workshop, July
7-9, 1997, Crete, Greece,
pp.
218-222.
Σ3.
H.
T. Vergos, D. Niκolos,
P. Mitsiadis, C. Kavousianos "Reconfigurable
CPU Cache Memory Design: Fault Tolerance and
Performance Evaluation", VLSI:
Integrated Systems on Silicon,
August 26-29, 1997
, Charman & Hall, pp. 103-114.
Σ4.
X.
Kavousianos,
D. Nikolos "Self-Exercising
k-order Comparators Based on Built-In Current
Sensing" Brazilian Symposium on Integrated Circuit Design, August 25-27,
1997, Gramado, Brazil, pp. 205-214.
Σ5.
X.
Kavousianos,
D. Nikolos, G. Sidiropoulos, "Design
of Compact and High Speed Totally Self-Checking
CMOS checkers for m-out-of-n Codes", IEEE
International Symposium on Defect and Fault
Tolerance in VLSI Systems, October 20-22,
1997, Paris, France,
pp.
128-136.
Σ6.
X.
Kavousianos,
D. Nikolos "Novel
Single and Double Output TSC Berger Code Checkers"
IEEE VLSI
Test Symposium, 1998,
Monterey
,
California
,
pp.
348-353.
Σ7.
D.
Nikolos & X. Kavousianos, "Efficient
Highly Testable Borden Code Checkers", IEEE
European Test Workshop, May 1998, Sitges,
Spain,
pp.
246-250.
Σ8.
X.
Kavousianos
& D. Nikolos, "Novel
TSC Checkers for Bose-Lin and Bose Codes",
IEEE
International On-Line Testing
Workshop, July 6-8, 1998,
Capri
,
pp.
172-176.
Σ9.
X.
Kavousianos,
D. Nikolos & S. Tragoydas, "On-Chip
Deterministic Counter-Based TPG with Low Heat
Dissipation", Southwest
Symposium on Mixed-Signal Design, April 11-13,
1999, Tuscon, Arizona, U.S.A,
pp.
87-92.
Σ10.
X.
Kavousianos,
D. Nikolos "Modular
TSC Checkers for Bose-Lin and Bose Codes",
IEEE VLSI
Test Symposium, April 25-29, 1999,
Dana
Point
,
pp.
354-360.
Σ11.
D.
Bakalis,
H.T.
Vergos,
D.
Nikolos,
X.
Kavousianos
& G.
Ph.
Alexiou,
"Low
power Dissipation in BIST Schemes for Modified
Booth Multipliers", IEEE
International Symposium on Defect and Fault
Tolerance in VLSI Systems, November 1-3, 1999,
New Mexico, USA, pp. 121-129.
Σ12.
D.
Bakalis, D. Nikolos & X. Kavousianos,
"Test
Response Compaction by an Accumulator Behaving as
a Multiple Input Non-Linear Feedback Shift
Register", International
Test Conference, Atlantic City, USA, October 1
– 6, 2000,
pp.
804-811.
Σ13.
X.
Kavousianos,
D. Bakalis & D. Nikolos, "A
Novel Reseeding Technique for Accumulator-based
Test Pattern Generation",
ACM Great Lakes Symposium on VLSI,
West Lafayette, USA, March 22-23, 2001, pp. 7-12.
Σ14.
D.
Bakalis, D. Nikolos,
H. T. Vergos
& X. Kavousianos, "On
Accumulator- based Bit-Serial Test Response
Compaction Schemes", IEEE
International Symposium on Quality Electronic
Design, San Jose, CA, USA, March 26-28, 2001,
pp.
350-355.
Σ15.
E.
Kalligeros, X. Kavousianos, D, Bakalis and
D. Nikolos, "A
New Reseeding Technique for LFSR-based Test
Pattern Generation", IEEE International On-Line Testing Workshop, Taormina, Italy, July
9-11,2001, pp. 80-86.
Σ16.
S.
J. Piestrak, D. Bakalis and X. Kavousianos,
"On
the Design of Self-Testing Checkers for Modified
Berger codes", IEEE
International On-Line Testing Workshop,
Taormina
,
Italy
, July 9-11, 2001, pp. 153-157.
Σ17.
E.
Kalligeros, X. Kavousianos, D, Bakalis and
D. Nikolos, "An
Efficient Seeds Selection Method for LFSR based
test-per-clock BIST", IEEE
International Symposium on Quality Electronic
Design, San Jose, March 18-21,
2002,
pp.261-266.
Σ18.
E.
Kalligeros, X. Kavousianos & D. Nikolos
"A
ROMless LFSR Reseeding Scheme for Scan-based BIST ",
IEEE Asian
Test Symposium,
Guam
, Nov. 18-20 2002, pp. 206-211.
Σ19.
G.
Dimitrakopoulos, X. Kavousianos & D.
Nikolos "Virtual-Scan:
A Novel Approach for Software-Based Self-Testing
of Microprocessors", International Symposium on Circuits and Systems, Vol.: 5,
May 25-28, 2003
pp. 237 -240
Σ20.
E.
Kalligeros, X. Kavousianos & D. Nikolos
"A
Highly Regular Multiphase Reseeding Technique for
Scan-based BIST", ACM
Great Lakes
Symposium on VLSI,
Washington DC, April 28-29, 2003,
pp
295-298.
Σ21.
M.
Bellos, X. Kavousianos, D. Kagaris & D.
Nikolos, "DV-TSE:
Difference
Vector Based Test Set Embedding", IFIP WG 10.5 Conference on Very Large
Scale Integration of System-on-Chip,
Dec.
1-3 2003,
Darmstadt,
Germany, pp. 343-348.
Σ22.
M.
Bellos, D. Bakalis, D. Nikolos and X.
Kavousianos, “Low
Power Testing by Test Vector Ordering With Vector
Repetition”, IEEE
International Symposium on Quality Electronic
Design, San Jose, CA, USA, March 22-24, 2004,
pp. 205-210,.
Σ23.
X.
Kavousianos,
D. Bakalis, M. Bellos and D. Nikolos, “An
Efficient Test Vector Ordering Method for Low
Power Testing”, IEEE Computer Society Annual Symposium on VLSI,
Louisiana
,
USA
, Febr. 19-20, 2004, pp. 285-288.
Σ24.
E.
Kalligeros, D. Kaseridis, X. Kavousianos
and D. Nikolos “Reseeding-based
Test Set Embedding with Reduced Test Sequences”,
IEEE
International Symposium on Quality Electronic
Design, San Jose, 21-23 March 2005, pp.
226-231.
Σ25.
D.
Kaseridis, E. Kalligeros, X. Kavousianos
and D. Nikolos “An
Efficient Test Set Embedding Scheme with Reduced
Test Data Storage and Test Sequence Length
Requirements for Scan-based Testing”, IEEE
European Test Symposium, Tallinn,
Estonia,
May 22-25, 2005, pp. 147-150.
Σ26.
M.
Bellos, D. Bakalis, D. Nikolos and X.
Kavousianos, “Vector
Repetition and Modification for Peak Power
Reduction in VLSI Testing”, IEEE
Workshop on Design and Diagnostics of Electronic
Circuits and Systems, Sopron, Hungary, April
13 - 16, 2005, pp. 160-165.
Σ27.
G.
Gekas, D. Nikolos, E. Kalligeros and X.
Kavousianos, “Power
Aware Test-Data Compression for Scan-Based Testing”,
IEEE
International Conference on Electronics, Circuits
and Systems, Gammarth, Tunisia, December
11-14, 2005.
Σ28.
X.
Kavousianos, E. Kalligeros and D. Nikolos, “Efficient
Test-Data Compression for IP Cores Using
Multilevel Huffman Coding”, Design,
Automation and Test in Europe Conference and
Exhibition, March 6-10, 2006, pp. 1033-1038.
Σ29.
E.
Kalligeros, X. Kavousianos and D. Nikolos,
“Efficient
Multiphase Test Set Embedding for Scan-based
Testing”, IEEE International
Symposium on Quality
Electronic
Design,
San
Jose, March
2006, pp. 433-438.
Σ30.
X.
Kavousianos,
E. Kalligeros
and D. Nikolos, “A
Parallel Multilevel-Huffman Decompression Scheme
for IP Cores with Multiple Scan Chains”,
Inf. Digest
IEEE European Test Symposium, 2006, pp. 164-169.
Σ31.
X.
Kavousianos,
E. Kalligeros
and D. Nikolos, “Test-Data
Compression Based on Variable-to-Variable Reusable
Huffman Coding”,
in Inf. Dig. of IEEE
European Test Symposium, 2007,
pp. 253-258.
Σ32.
V.
Tenentes, X. Kavousianos and E. Kalligeros,
“State
Skip LFSRs: Bridging the Gap between Test Data
Compression and Test Set Embedding for IP cores”,
in Design,
Automation and Test in
Europe
Conference and Exhibition, March
10-14, pp. 474-479, 2008.
Σ33.
V.
Tenentes, X. Kavousianos and
E. Kalligeros
, “Shrinking
the Application Time of Test Set Embedding by
Using Variable-State Skip LFSRs”, in Inf.
Dig. of
ΙΕΕΕ European Test
Symposium, 2008
Σ34.
A.
Floros, Y. Tsiatouhas and X. Kavousianos, “The
Time Dilation Scan Architecture for Timing Error
Detection and Correction”, Proc.
of IFIP/
IEEE
International Conference on Very Large Scale
Integration, (VLSI-SoC08), pp. 569-574, Oct.
2008.
Σ35.
X.
Kavousianos, K. Chakrabarty, " Generation
of Compact Test Sets with High Defect Coverage"
Proc. of Design
Automation
and Test in Europe Conference and Exhibition,
pp. 1130-1135, Apr. 2009
Σ36.
M.
Koutsoupia, E. Kalligeros, X. Kavousianos,
D. Nikolos, " LFSR-based
Test-Data Compression with Self-Stoppable Seeds",
Proc.
of
Design Automation
and Test in Europe Conference and Exhibition,
pp. 1482-1487, Apr. 2009
Σ37.
S.
Balatsouka, V. Tenentes, X. Kavousianos, K.
Chakrabarty, "Defect
Aware X-Filling for Low-Power Scan Testing",
in Design
Automation
and Test in Europe Conference and Exhibition,
2010, pp. pp. 873-878
Σ38.
V.
Tenentes, X. Kavousianos, “Self-Freeze
Linear Decompressors for Low Power Testing”,
in IEEE
Annual Symposium on VLSI, 2010,
pp. 63-68.
Σ39.
X.
Kavousianos, K. Chakrabarty, E. Kalligeros and V.
Tenentes, " Defect
Coverage-Driven Window-Based Test Compression",
IEEE
Asian Test Symposium, 2010, pp. 141-146, 2010
Σ40.
Z.
Wang, X. Kavousianos, Y. Tsiatouhas and K.
Chakrabarty, "A Robust and Reconfigurable
Multi-Mode Power Gating Architecture", 24th
International Conference in VLSI Design pp. 280-285, 2011.
Σ41.Z. Zhang, X.
Kavousianos, Y. Luo, Y. Tsiatouhas and K.
Chakrabarty, "Signature
Analysis for Testing, Diagnosis, and Repair of
Multi-Mode Power Switches”, IEEE
European Test Symposium, pp. 13-18, 2011.
Σ42.
Z.
Zhang, X. Kavousianos, Y. Tsiatouhas and K.
Chakrabarty, “A
BIST Scheme for Testing and Repair of Multi-Mode
Power Switches”, IEEE On-Line
Test Symposium, pp. 115-120, 2011.
Σ43. V.
Tenentes, X.
Kavousianos, “Test-Data Volume and Scan-Power
Reduction with Low ATE Interface for Multi-Core
SoCs” to be presented in 2011 International
Conference on Computer-Aided Design (ICCAD)
Σ44. X. Kavousianos,
K. Chakrabarty, A. Jain, R. Parekhji, "Test
Scheduling for Multicore SoCs with Dynamic Voltage
Scaling and Multiple Voltage Islands",
accepted for presentation in IEEE Asian Test
Symposium 2011.
Σ45.V. Tenentes, X. Kavousianos, "Power
Test-Compression for High Test-Quality and Low
Test-Data Volume", accepted for presentation
in IEEE Asian Test Symposium 2011.
Fast Abstracts
G. Dimitrakopoulos, X. Kavousianos & D. Nikolos
"Software-Based
Self-Testing of Microprocessors by Exploiting a
Virtual Scan Path", European
Dependable Computing Conference, Oct 23-25, 2002, Toulouse,
France, pp.23-24.
